Fault Tolerant Memory In Processor - SuperComputer On a Chip
نویسندگان
چکیده
Soft errors are adding another dimension to the present day architecture design space. Different techniques like redundant multithreading are evolved for handling them. The Memory In Processor (MIP) architecture provides fine grain processor memory integration. This integration provides efficient support for redundant multithreading within a functional unit. Detecting errors in intermediate stage of functional units reduces flushing of incorrect results and provides competent support for error recovery. As interconnect dominance increases, parasitics-induced phenomenons (i.e crosstalk) cause increased errors in bus lines. We integrate the Error Correction Codes (ECC) in the execution pipeline to protect results from faults occurring during transmission.
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